1. Field of the Invention
The present invention relates to a clocking scheme for electronic circuitry, such as phase-locked loops (PLL).
2. Background Information
In large chips employing binary digital signals or bits, such as, without limitation, microprocessors, microcontrollers, digital signal processors, ASICs and others, a significant amount of power is dissipated due to the clock signal driving the chip components. More specifically, the clock signal is typically distributed via a clock tree network. The clock signal drives a relatively large value of capacitance due to the presence of input capacitances for the devices used to construct register and latches, for example. Without limitation, a capacitance might be approximately in the range of a nanofarad to tens or hundreds of nanofarads, for example.
Typically, the clock signal is produced using a phase-locked loop (PLL) FIG. 3 is a schematic diagram illustrating a conventional phase-locked loop. Likewise, this particular PLL comprises a charge pump PLL. As illustrated in FIG. 3, a voltage-controlled oscillator (VCO) 310 produces a VCO output clock signal C2. VCO output clock signal C2 may be fed back directly or through a divider 320 (shown using a dotted line) if frequency multiplication is employed, although the following discussion assumes no divider. Phase detector 330 compares the phase and frequency of VCO clock signal C2 with the phase and frequency of reference clock signal C1. Based upon the phase delay between the two clock signals, phase detector 330 produces an up signal and a down signal. These different signals are produced by different output ports of phase detector 330. As illustrated in FIG. 3, these up and down signals are applied to control switches of a charge pump that will short circuit an electrical path including a current source, such as current sources 340 and 350. Thus, as illustrated in FIG. 3, when these switches close, current flow charges or discharges capacitor 360. Therefore, depending upon the duration of the up signal and the down signal produced by phase detector 330, the voltage of capacitor 360 may be adjusted. By adjusting the duration of the signals applied, the voltage across capacitor 360 may either increase or decrease. Furthermore, as illustrated in FIG. 3, capacitor 360 is coupled to voltage-control oscillator 310 so that the frequency of the output clock signal produced by VCO 310 will be adjusted in response to the voltage across capacitor 360. Therefore, a delay between VCO clock signal C2 and reference clock signal C1 should become smaller based, at least in part, on the negative feedback operation of the PLL. When the output clock signal of VCO 310 closely matches reference clock signal C1 in phase and frequency, the PLL is "locked".
In this embodiment, block 345 is referred to as a charge pump, although block 340 also includes a filter in the form capacitor 360, and in some embodiments the filter is indicated separately from the charge pump. Likewise, in this context, the term charge pump refers to any circuit that produces a VCO control voltage based at least in part on the phase detector output signal. Furthermore, this term is employed in this context even if the circuit is entirely digital.
FIG. 2 illustrates the basic structure of a conventional clock tree 200 to distribute the clock signal to the chip components. In FIG. 2, 210 comprises a PLL, such as previously discussed with reference to FIG. 3. As illustrated, a feedback clock signal and a reference clock signal are applied to PLL 210. This clock tree has a number of drivers, such as 220, 230, 240, 250, 260, 270 and 280, and may progressively get larger, to drive large capacitances, such as attributable to registers and latches, with the output signal of the voltage-controlled oscillator of the phase-locked loop (PLL). These drivers typically contain inverters (not shown). Hence, the capacitances are being switched at the clock frequency. The capacitances illustrated in FIG. 2 as 265, 275, 285, 290, 295 and 255 are the capacitances attributable to the components of the chip, in this example. In addition to these capacitances, the gate capacitances of the driver inverters are also switching at the clock frequency. If the total capacitance for the clock network is represented as C and the clock network switches at the clock frequency, f, the amount of power dissipated may be represented as CV.sup.2 f, where V is the supply voltage. This amount of power may be a significant portion of the total power utilized by the chip due to a relatively large C and a relatively high f. A need, therefore, exists for a technique of reducing the amount of power dissipated in a chip employing digital circuitry, due to the particular clocking scheme employed.